Dynamic ram

ABSTRACT

A refresh switching circuit for a dynamic RAM which is capable of easily switching a RAS-only refresh to a CAS-before-RAS refresh, thereby consuming less electric power, easily executing a shift to a self-refresh (suspending), and obtaining comparability with conventional personal computer systems. The dynamic RAM comprises a CPU (101), dynamic RAM arrays (115) and a system logic (110) for use in a microprocessor system, and further comprises a refresh switching circuit (111) for switching the RAS-only refresh to the CAS-before-RAS refresh.

Technical Field of the Invention

The present invention relates to a refresh switching circuit for adynamic RAM (Random Access Memory) such as that commonly used as thememory device for a personal computer.

BACKGROUND OF THE INVENTION

A main memory device in a personal computer includes for general usethereof a dynamic RAM which is advantageous in view of the unit costthereof in a memory capacity. Memory capacities of semiconductors areincreased with the technical progress thereof, thereby reducing the sizeof personal computers.

A dynamic RAM is needed to be routinely refreshed for holding any datastored therein.

Conventional personal computers employ a RAS (Row Address Strobe)-onlyrefresh procedure as a most standard technique wherein a CAS (ColumnAddress Strobe) signal is set to a high level and a RAS signal is variedin conformity with refresh addresses applied to an address terminal, andrefresh is achieved by selecting all refresh addresses. The RAS-onlyrefresh procedure is a common refresh technique for systems usingdynamic RAMs.

The RAS signal serves to latch a row address supplied from the outsideto select the row of a memory cell of a dynamic RAM in an internal rowaddress decoder.

The CAS signal serves to latch a column address supplied from theoutside to select the column of a memory cell of a dynamic RAM in aninternal column address decoder.

With reference to the accompanying drawings, the read/write operation ofa dynamic RAM and the RAS-only refresh procedure will be described.

As illustrated in FIG. 1, a central processing unit (hereinafterreferred to as a CPU) 401 reads data from and writes data into a dynamicRAM array 411. Although a system logic control unit is typicallyconsidered part of the CPU, the system logic will be referred toseparately to facilitate an understanding of the read/write and refreshprocedures for the dynamic RAM. The CPU 401 provides a read or writeaddress to a CPU address bus 405 and further provides a CPU statussignal 403 to instruct a system logic 406 to read/write the datafrom/into the dynamic RAM array 411.

The system logic 406 transmits the address provided from the CPU addressbus 405 onto a memory address bus 407 as a row address and a columnaddress of the dynamic RAM.

The system logic 406 further switches the RAS signal 408 from a "H"level to a "L" level while providing the row address, thereby latchingthat signal in the dynamic RAM array 411 as the row address of thedynamic RAM.

Thereafter, the system logic 406 switches the CAS signal 409 from a "H"level to a "L" level while providing the column address,, therebylatching that signal in the dynamic RAM array 411 as the column addressof the dynamic RAM.

At that time, if the CPU status signal 403 from the CPU 401 is aninstruction to write associated data into the dynamic RAM, a WE (WriteEnable) signal 410 is switched from "H" to "L" level, therebytransferring the write data on the CPU data bus 402, provided from theCPU 401, into the dynamic ]RAM array 411.

In contrast, if the CPU status signal 403 from the CPU 401 is aninstruction to read associated data from the dynamic RAM, then after ashort delay, data from the dynamic RAM array 411 is outputted on the CPUdata bus 402 and is received by the CPU 401. The system logic 406coordinates the timing of the receiving of the read data by the CPU 401via a ready signal 404.

The foregoing is a description of the read/write operation by the CPU401 from/into the dynamic RAM array 411.

The system logic 406 must refresh the dynamic RAM array 411 within apredetermined time interval while the CPU 401 reads/writes associateddata from/into the dynamic RAM array 411.

The system logic 406 includes therein a circuit for generating rawaddresses, which serves to interrupt the CPU 401 during eachpredetermined time interval by providing a row address for output to thememory address bus 407 while the RAS signal 408 is switched from the "H"level to the "L" level, maintaining the CAS signal 409 at the "H" level.

The aforementioned refreshing technique is called a RAS-only refresh.Referring to FIG. 2, there is illustrated a timing relationship betweenthe RAS signal 408 and the row address in the RAS-only refresh.

As illustrated in FIG. 2, prior to the RAS signal 408 being switchedfrom the "H" level to the "L" level, a row address has previously beenstabilized on the memory address bus 407, and when the RAS signal 408 isswitched from the "H" level to "L" level, the row address is latched inthe dynamic RAM array 411.

Thereafter, the data stored in the dynamic RAM at the designated rowaddresses are read out therefrom, and are again stored at their originaladdresses when the RAS signal is switched from the "L" to "H" level.

Such a RAS-only refresh technique described above with reference toFIGS. 1 and 2 is relatively simplified in its control, and hence isuseful in many personal computers (those from IBM and compatible onestherewith). Accordingly, manufacturers of the system logic 406 of FIG.1, which controls the refreshing of a dynamic RAM, all adopt theRAS-only refresh technique. This is inevitably required for ensuringcompatibility of associated systems.

RAS-only refreshing, however, suffers from problems such as having alarge consumed current when data holding (suspending) by the dynamic RAMarray is performed, even while restricting to the minimum the total ofconsumed currents other than that in the dynamic RAM array. The systemlogic, which controls the refresh addressing, needs to generate arefresh address even during the suspension and hence requires ordinaryoperation. This results in the large consumed current during thesuspension.

Most portable personal computers include systems driven by a battery andoften enjoy the use of a large capacity dynamic RAM as a main memory.Such systems driven by a battery, however, have difficulty in that theirbattery charge life is severely reduced because of the consumed currentnecessary for the RAS-only refresh.

There is known for dynamic RAMs CAS-before-RAS refreshing which isaccomplished with a relatively less consumed current. Referring to FIG.3, there will be described the CAS-before-RAS refresh.

The CAS-before-RAS refresh is such that a CAS signal is switched from a"H" level to a "L" level before a RAS signal is switched from a "H"level to a "L" level, and the operation enters a CAS-before-RAS refreshcycle provided the CAS signal remains at the "L" level even after theRAS signal is altered from the "H" to "L" level.

The CAS-before-RAS refresh technique does not need a refresh address tobe supplied from the system logic, as does the RAS-only refresh.Instead, a row of the dynamic RAM is designated by a refresh addressgenerated by a counter included in the dynamic RAM.

The CAS-before.-RAS refresh is further advantageous in that it is easilychanged to the self-refresh operation. The self-refresh enjoys the leastconsumed current and is suitable for data holding by a dynamic RAM.

Referring to FIG. 4, there will be described the self-refresh.

As understood from FIG. 4, the self-refresh operation toggles the RASsignal between the "H" level and the "L" level while the CAS signalremains at the "L" level. This results in the least consumed currentduring data holding by the dynamic RAM.

It is further possible to transfer the operation with ease from theCAS-before-RAS refresh to the self-refresh, and vice versa.

In operation, an actual measurement of the mean consumed current uponrefreshing reads 80 mA for the RAS-only refresh, 60 mA for theCAS-before-RAS refresh, and 30 mA for the self-refresh.

In prior art systems, many personal computers which support only theRAS-only refresh are obliged to use the RAS-only refresh technique,which is burdened with the greatest consumed current during data holdingby the dynamic RAM.

When the RAS-only refresh is used, transferring to self-refresh for dataholding by the dynamic RAM is very difficult. The reason for this isthat a refresh address during the RAS-only refresh is suppliedexternally of the dynamic RAM array 411, as illustrated in FIG. 1, whilea refresh address during the self-refresh is supplied from a counterincluded in the dynamic RAM array 411. This causes a discontinuouschange in refresh addresses upon the operation being switched from theRAS-only refresh to the self-refresh.

The present invention has been made in view of the foregoingcircumstances, and has for its object to provide a refresh switchingcircuit of a dynamic RAM wherein the prior art RAS-only refresh isswitched to the CAS-before-RAS refresh, which consumes less current, andthe dynamic RAM is then easily transferred to self-refresh for dataholding (suspension). Furthermore, the refresh switching circuit iscompatible with prior art personal computer systems in regard to bothhardware and software.

SUMMARY OF THE INVENTION

To achieve the above objects of the present invention, there is provideda dynamic RAM in a microprocessor system comprising a central processingunit, a dynamic RAM array, and a system logic, which is characterized byincluding a refresh switching circuit for switching RAS-only refresh toCAS-before-RAS refresh when RAS-only refresh is executed for the dynamicRAM array.

In the dynamic RAM set forth above, the refresh switching circuit canalso perform a switching operation between the CAS-before-RAS refreshand a self-refresh, thereby suspending the data held by the dynamic RAMwith less power consumption.

Further, in the dynamic RAM set forth above, the refresh switchingcircuit comprises an external terminal for inputting a clock signal witha cycle time within the allowable range of data holding times for thedynamic RAM array, thereby enabling the dynamic RAM to perform therefresh operation even when both the central processing unit and thesystem logic are stopped.

The above and many other advantages, features, and additional objects ofthe present invention will become manifest to those versed in the artupon making reference to the following detailed description andaccompanying drawings in which preferred embodiments incorporating theprinciples of the present invention are shown by way of illustrativeexample.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating the arrangement of a prior artdynamic RAM;

FIG. 2 is a timing chart illustrating RAS-only refresh;

FIG. 3 is a timing chart illustrating CAS-before-RAS refresh;

FIG. 4 is a timing chart illustrating the operation of the prior artwhen the operation is switched from CAS-before-RAS refresh toself-refresh and then returned to CAS-before-RAS refresh;

FIG. 5 is a circuit diagram illustrating the arrangement of a dynamicRAM with a refresh switching circuit;

FIG. 6 is a timing chart illustrating RAS-only refresh issued by asystem logic to a refresh switching circuit;

FIG. 7 is a timing chart illustrating a conversion from RAS-only refreshto CAS-before-RAS refresh by the refresh switching circuit;

FIG. 8 is a circuit diagram illustrating the refresh switching circuitof the present invention; and

FIG. 9 is a timing chart illustrating a conversion from CAS-before-RASrefresh to self-refresh and then back to CAS-before-RAS refresh.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be described withreference to FIGS. 5 to 9.

As illustrated in FIG, 5, the dynamic RAM of the present inventioncomprises a CPU 101, a system logic 110 for controlling a dynamic RAMarray 115 on the basis of an instruction from the CPU 101, and a refreshswitching circuit 111 for switching RAS-only refresh issued from thesystem logic 110 to the dynamic RAM array 115 to CAS-before-RAS refresh.

When the CPU 101 of FIG. 5 desires to access the dynamic RAM array 115to read/write data from/into the same, the CPU 101 transmits aread/write address onto a CPU address bus 102, end provides a read/writeinstruction to the system logic 110 through a CPU status signal 117.

The system logic 110 separates the address transmitted through the CPUaddress bus 102 into a row address and a column address for the dynamicRAM array 115 and transfers those addresses onto a memory address bus113.

The system logic 110 further switches a RAS signal 106 from the "H"level to the "L" level while transmitting the row address.

The refresh switching circuit 111, as receiving the RAS signal 106changing from the "H" to "L" level, switches a RASN signal 112, alteredto the CAS-before-RAS refresh format, from the "H" to "L" level, therebylatching the transmitted row address into the dynamic RAM array 115.

Thereafter, the output from the system logic 110 is altered from the rowaddress to the column address, and a CAS signal 107 is changed from the"H" level to the "L" level.

The refresh switching circuit 111, as receiving the CAS signal 107changing from the "H" level to the "L" level, switches a CASN signal114, altered to the CAS-before-RAS refresh format, from a "H" level to a"L" level, thereby latching the transmitted column address into thedynamic RAM array as the column address of the dynamic RAM.

If the CPU status signal 117 from the CPU 101 is an instruction to writedata into the dynamic RAM array 115, a WE (Write Enable) signal 109 ischanged from a "H" level to a "L" level, thereby writing the data on theCPU data bus 103, provided from the CPU 101, into the dynamic RAM array115.

If the CPU star,us signal 117 from the CPU 101 is an instruction to readdata from the dynamic RAM array 115, then read data residing in thedynamic RAM, the location of which having been specified by the row andcolumn addresses provided by the system logic 110, is transmitted ontothe CPU data bus 103 and is received by the CPU 101 as read data. In thecase where the data read out from the dynamic RAM array 115 is outputtedwith a delay, the system logic 110 coordinates the timing of the CPU 101incorporating the read data from the CPU data bus 103 by way of a READYsignal 118.

The foregoing is a description of the read/write operation of the CPU101 from/into the dynamic RAM array 115.

In accordance with the present invention, the RAS-only refresh in theprior art personal computers is switched to the CAS-before-RAS refreshthrough the refresh switching circuit, thereby allowing the operation tobe further transferred with ease to self-refresh (suspension) by thedynamic RAM while maintaining compatibility with the prior art personalcomputer systems in regard to both hardware and software.

Hereinafter, a circuit arrangement of the refresh switching circuitillustrated in FIG. 5 will be described with reference to a circuitdiagram illustrated in FIG. 8.

As illustrated in FIG. 8, the RAS signal 106 is fed to respective inputterminals of a gate G701 and a composite gate G714. The other inputterminal of the gate G701 is fed from an external terminal (EXT) with asignal on signal line L767 which acts in a manner similar to the RASsignal 106 during the self-refresh. The other input terminal of thecomposite gate G714 is connected to the output signal line L764 from aninverter G713.

The CAS signal is fed to an input terminal of a composite gate G717. Theother input terminal of the composite gate G717 is fed by the outputsignal on the output signal line L764 from the inverter G713.

A HOLDA signal 104, indicative of permission to refresh, is entered to,the input terminal of an inverter G722 and to an input terminal of agate G710.

A REFRESHN signal 105, indicative of the operation being in refreshmode, is entered to an input terminal of a gate G703 and to the inputterminal of a delay element G702.

An output signal on a signal line L753 from the inverter G722 is enteredto an input terminal of the gate G703 and to an input terminal of a gateG704.

Further, an output signal from the gate G701 is entered to an inputterminal of the gate G704.

An output signal on a signal line L752 from the delay element G702 isentered to an input terminal of the gate G704.

A signal line L768 connected between input terminals of the gate G703and the gate G704 is connected to ground potential.

Further, an output signal line L754 of the gate G703 is connected to aninput terminal of a gate G712.

An output signal line L755 of the gate G704 is connected to an inputterminal of a gate G711, to the input terminal of a delay element G709,to the clock terminal of a flip-flop G705, and to the input terminal ofan inverter G708.

A data holding SUSPEND signal line 108 is connected to the inputterminal of an inverter G723.

A RESET signal line 116 is connected to the reset terminal of theflip-flop G705 and to the reset terminal of a flip-flop G706.

An output signal line L756 of the inverter G723 is connected to the dataterminal of the flip-flop G705.

A Q output signal line L757 of the flip-flop G705 is connected to thedata terminal of the flip-flop G706.

A QB output signal line L758 of the flip-flop G705 is connected to aninput terminal of a gate G707.

A QB output signal line L760 of the flip-flop G706 is connected to aninput terminal of the gate G707.

An output signal line L759 of the inverter G708 is connected to theclock terminal of the flip-flop G706.

An output signal line L769 of the delay element G709 is connected to aninput terminal of a gate G710.

An output signal line L761 of the gate G707 is connected to an inputterminal of the gate G711 and the gate G712.

An output signal line L770 of the gate G710 is connected to an inputterminal of a composite gate G715.

An output signal line L762 of the gate G711 is connected to an inputterminal of a composite gate G718.

An output signal line L763 of the gate G712 is connected to an inputterminal of the composite gate G718, to an input terminal of thecomposite gate G715, and to the input terminal of the inverter G713.

An output terminal of the composite gate G714 and an output terminal ofthe composite gate G715 are part of a composite gate construction andare directly connected to the input terminals of a composite gate G716.

An output signal line L765 of the composite gate G716 is connected tothe input terminal of an inverter G720, the output terminal of whichprovides a RASN signal 112.

An output terminal of the composite gate G717 and an output terminal ofthe composite gate G718 are part of a composite gate construction andare directly connected to the input terminals of a composite gate G719.

An output signal line L766 of the composite gate G719 is connected tothe input terminal of an inverter G721, the output terminal of whichprovides a CASN signal 114.

The gate G701 comprises a 2-input AND gate and the gates G711 and G712comprise 2-input NOR gates. The gate G710 and the gate G707 comprise2-input NAND gates, and the gate G703 comprises a 3-input NOR gate. Thegate G704 comprises a 4-input NOR gate, and the flip-flops G705 and G706comprise D flip-flops.

Further, the composite gates G714 and G715 comprise 2-input NOR gates,and the composite gate G716 comprises a 2-input OR gate. The compositegates G717 and G718 comprise 2-input NOR gates, and the composite gateG719 comprises a 2-input OR gate.

The delay elements G702 and G709 comprise integration circuits and serveto delay their respective input signals.

The inverter G720 and the inverter G721 serve to drive the dynamic RAMarray 115 illustrated in FIG. 5.

There will now be described a circuit operation for the refreshswitching circuit illustrated in FIG. 8.

As shown in FIGS. 8, the signal line L764 is of the "L" level exceptduring the refresh mode, so that the RAS signal 106 and the CAS signal107 satisfy gate conditions of the composite gate G714 and of thecomposite gate G717, respectively, when latching row and columnaddresses into the dynamic RAM array. Accordingly, a signal on theoutput signal line L765 of the composite gate G716 is inputted to theinverter G720, and the RASN signal 112 is provided on the outputterminal of the inverter G720 to drive the dynamic RAM array 115illustrated in FIG. 5. Similarly, the signal on the output signal lineL766 of the composite gate G719 is inputted to the inverter G721, andthe CASN signal 114 is provided on the output terminal of the inverterG721 to drive the dynamic RAM array 115.

The refresh switching circuit 111 illustrated in FIG. 5 is thereforeoperated as in the prior art example during the read/write operation ofthe CPU 101 from/into the dynamic RAM array 115.

The system logic 110 instructs the dynamic RAM array 115 to execute theRAS-only refresh after the lapse of a predetermined time. At that time,the refresh switching circuit 111 may switch the operation from theRAS-only refresh to the CAS-before-RAS refresh to refresh the dynamicRAM array 115.

Next, the circuit operation of the refresh switching circuit 111 will bedescribed with reference to the waveform diagrams shown in FIGS. 6 and7.

Referring to FIG. 6, there is illustrated a timing relationship amongthe HOLDA signal 104, indicative of permission by the system logic 110to refresh, the REFRESHN signal 105, indicative of the system logic 110being in the refresh mode, the RAS signal 106, and the CAS signal 107.The refresh switching circuit 111 executes the RAS-only refresh in thistiming.

Referring to FIG. 7, there is illustrated a timing chart which indicatesa process where the RAS-only refresh is switched to the CAS-before-RASrefresh.

There will next be described a switching operation indicated by thearrow 1 in FIG. 7 and with further reference to FIG. 8.

As shown in FIG. 8, when the HOLDA signal 104 stays at the "H" level,the REFRESHN signal 105 stays at the "L" level, and the RAS signal 106is changed from the "H" level to the "L" level, the output signal on theoutput signal line L754 of the gate G703 is changed to the "H" level andthe output signal on the output signal line L763 of the gate G712 ischanged to the "L" level.

Thereafter, the output signal on the output signal line L755 of the gateG704 becomes the "H" level and the output signal on the output signalline L762 of the gate G711 becomes the "L" level. At that time, logicalconditions of the composite gate G718 are satisfied, and therefore theCASN signal 114 becomes the "L" level.

The reason why the delay element G702 is inserted between the REFRESHNsignal 105 input and an input to gate G704 is that there exists such atime when the HOLDA signal 104 is at the "H" level, the REFRESHN signal105 is at the "H" level, and the RAS signal 106 is at the "L" level. Inorder to to discriminate the RAS signal 106 at this time from the RASsignal 106 during a refresh, the REFRESHN signal 105 is delayed throughthe delay element G702.

The just-mentioned timing, in which the HOLDA signal 104 is at the "H"level, the REFRESHN signal 105 is at the "H" level, and the RAS signal106 is at the "L" level, is produced just before the operation entersthe refresh mode.

Next, there will be described a switching operation indicated by thearrow 2 in FIG. 7 with further reference to FIG. 8.

The output signal on the output signal line L755 of the gate G704 isdelayed through the delay element G709, after which the output signal onthe output signal line L770 of the gate G710 becomes the "L" level tosatisfy the logical condition of the composite gate G715 to permit theRASN signal 112 to become the "L" level.

The RASN signal 112 becomes the "L" level later than the CASN signal 114as a result of the delay element G709.

Similarly, the RASN signal 112 becomes the "H" level later than the CASNsignal 114, again as a result of the delay element G709, and at thistime, the switching of the RAS-only refresh to the CAS-before-RASrefresh is completed.

By this operation, the dynamic RAM array 115 is refreshed by the RASNsignal 112 and the CASN signal 114 as a result of the RAS signal 106being changed to the CAS-before-RAS refresh.

The CAS-before-RAS refresh is such that the CASN signal 114 is switchedfrom the "H" level to the "L" level before the RASN signal 112 isswitched, and the dynamic RAM enters the CAS-before-RAS refresh cycleprovided the CASN signal 114 stays at the "L" level even after the RASNsignal 112 is switched from the "H" level to the 37 L" level.

The above-described CAS-before-RAS refresh technique does not require arefresh address to be provided by the system logic 110 to the memoryaddress bus 113, but instead allows for a designated row to be refreshedon the basis of a refresh address generated by the counter in thedynamic RAM.

Next, there will be described a process for switching from theCAS.-before-RAS refresh to the self-refresh (suspension) by the dynamicRAM, and then returning to the CAS-before-RAS refresh. Reference is madeto the arrow 3 in FIG. 9 and to FIG. 8.

Such a refresh switching circuit, capable of switching fromCAS-before-RAS to self-refresh and vice versa, is comprised of thecircuit shown in FIG. 8 from which the gates G714 and G717 are omittedand in which the RAS signal 106 and the output of gate G715 are fed intothe inputs of gate G716, and in which the output of gate G718 is fedinto an input of the gate G719.

In this refresh switching circuit for implementing self-refresh, whenthe SUSPEND signal 108 becomes the "L" level, the output signal on theoutput signal line L761 from the gate G707 becomes the "H" level withthe rising of the output signal on the output signal line L755 from thegate G704, thereby satisfying the logical condition of the compositegate G718 and permitting the CASN signal 114 to become the "L" level.

The self-refresh is started in this manner, the dynamic RAM beingrefreshed each time the RASN signal 112 is cycled with the CASN signal114 at the "L" level.

In the self-refresh mode, when there is no input of the RAS signal 106,namely, when both the CPU 101 and the system logic 110 are inactive, aclock signal is fed from the external terminal (EXT) into an inputterminal of the gate G701. Accordingly, it becomes possible to hold datain the dynamic RAM array 115 with a remarkably lower consumed electricpower, provided that the clock input has a cycle time within theallowable range of data holding times in the dynamic RAM array 115.

Reference is now made to the switching operation indicated by the arrow4 in FIG. 9 with further reference to FIG. 8.

When the SUSPEND signal 108 is switched to the "H" level, the outputsignal on the output signal line L761 of the gate G707 becomes the "L"level at the falling of the output signal on the output signal line L755of the gate G704, thereby switching the CASN signal 114 to the "H"level. At this time, the self-refresh is complete and the operationreturns to the CAS-before-RAS refresh.

In the above-described switching circuit, switching between theCAS-before-RAS refresh and the self-refresh is easily achieved, therebyimplementing data holding (suspension) by the dynamic RAM with a lowerconsumed electric power.

It should be noted that the RESET signal 116 is switched to the "L"level at a time when the system power supply is on so as to initializethe electronic circuits such as the flip-flops.

Industrial Utility

As apparent from the above description of the present invention, apersonal computer incorporating the dynamic RAM of the present inventionwill enjoy a greatly reduced consumption of current through the personalcomputer when data holding by the dynamic RAM is performed.

Additionally, the dynamic RAM refresh circuit is compatible with theprior art personal computers in regard to both hardware and software.

What is claimed is:
 1. A dynamic RAM in a microprocessor systemincluding a central processing unit, a dynamic RAM array and a systemlogic, said dynamic RAM comprising a refresh switching circuit havingmeans for converting RAS-only refresh to CAS-before-RAS refresh inresponse to RAS and CAS signals when the RAS-only refresh is executedfor the dynamic RAM array.
 2. The dynamic RAM according to claim 1,wherein said refresh switching circuit has means for performing aswitching operation between said CAS-before-RAS refresh to achieve aself-refresh, thereby providing a data holding by said dynamic RAM witha lower consumed electric power.
 3. The dynamic RAM according to claim2, further comprising an external terminal for inputting therein a clocksignal having a periodic time within the allowable range of data holdingtimes in said dynamic RAM array, thereby enabling said dynamic RAM toperform the refresh operation even when both said central processingunit and said system logic are stopped.
 4. The dynamic RAM according toclaim 1, further comprising an external terminal for inputting therein aclock signal having a periodic time within the allowable range of dataholding times in said dynamic RAM array, thereby enabling said dynamicRAM to perform the refresh operation even when both said centralprocessing unit and said system logic are stopped.
 5. A refreshswitching circuit for a microprocessor system having a centralprocessing unit, a system logic, and a dynamic RAM array, said circuithaving means for converting a RAS-only refresh command from said systemto a CAS-before-RAS refresh, thereby reducing power consumed by saidsystem during a refresh operation.
 6. The switching circuit of claim 5wherein said circuit has means for passing a RAS signal there throughunchanged when said system is not performing a refresh operation.
 7. Theswitching circuit of claim 6 wherein said switching circuit includes anexternal terminal for inputting a clock signal, thereby permitting saidsystem to perform a refresh operation when said central processing unitand said system logic are inactive.
 8. The switching circuit of claim 5wherein said switching circuit includes an external terminal forinputting a clock signal, thereby permitting said system to perform arefresh operation when said central processing unit and said systemlogic are inactive.
 9. The switching circuit of claim 5 wherein saidswitching means includes means for converting said CAS-before-RASrefresh to a self-refresh, thereby further reducing the power consumedby said system during a refresh operation.
 10. The switching circuit ofclaim 9 wherein said circuit has means for passing a RAS signal therethrough unchanged when said system is not performing a refreshoperation.
 11. The switching circuit of claim 10 wherein said switchingcircuit includes an external terminal for inputting a clock signal,thereby permitting said system to perform a refresh operation when saidcentral processing unit and said system logic are inactive.
 12. Theswitching circuit of claim 9 wherein said switching circuit includes anexternal terminal for inputting a clock signal, thereby permitting saidsystem to perform a refresh operation when said central processing unitand said system logic are inactive.
 13. A method for refresh switchingin a microprocessor system, said system having a central processingunit, a system logic, a dynamic RAM array, and a refresh switchingcircuit, the method comprising the steps of:inputting a RAS signal tosaid switching circuit; and converting said RAS signal to CAS-before-RASrefresh signals when said system is in a refresh operation.
 14. Themethod of claim 13 further comprising the step of outputting said RASsignal from said circuit unchanged when said system is not in a refreshoperation.
 15. The method of claim 14 wherein said circuit includes anexternal terminal, and the method further comprises the step ofinputting a clock signal into said external terminal to thereby permitsaid system to perform a refresh operation when said CPU and said systemlogic are inactive.
 16. The method of claim 13 wherein said circuitincludes an external terminal, and the method further comprises the stepof inputting a clock signal into said external terminal to therebypermit said system to perform a refresh operation when said CPU and saidsystem logic are inactive.
 17. The method of claim 13 further comprisingthe step of converting said CAS-before-RAS refresh signals toself-refresh signals when said system is in a refresh operation.
 18. Themethod of claim 17 further comprising the step of outputting said RASsignal from said circuit unchanged when said system is not in a refreshoperation.
 19. The method of claim 18 wherein said circuit includes anexternal terminal, further comprising the step of inputting a clocksignal into said external terminal to thereby permit said system toperform a refresh operation when said CPU and said system logic areinactive.
 20. The method of claim 17 wherein said circuit includes anexternal terminal, and the method further comprises the step ofinputting a clock signal into said external terminal to thereby permitsaid system to perform a refresh operation when said CPU and said systemlogic are inactive.